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2 GHz Ultralow Distortion Differential RF/IF Amplifier AD8352
FEATURES
-3 dB bandwidth of 2.2 GHz (AV = 10 dB) Single resistor gain adjust: 3 dB AV 25 dB Single resistor and capacitor distortion adjust Input resistance: 3 k, independent of gain (AV) Differential or single-ended input to differential output Low noise input stage: 2.7 nV/Hz RTI @ AV = 10 dB Low broadband distortion 10 MHz: -86 dBc HD2, -82 dBc HD3 70 MHz: -84 dBc HD2, -82 dBc HD3 190 MHz: -81 dBc HD2, -87 dBc HD3 OIP3 of 41 dBm @ 150 MHz Slew rate: 8 V/ns Fast settling and overdrive recovery of <2 ns Single-supply operation: 3 V to 5.5 V Low power dissipation: 37 mA typical @ 5 V Power-down capability: 5 mA @ 5 V Fabricated using the high speed XFCB3 SiGe process
FUNCTIONAL BLOCK DIAGRAM
ENB RGP RDP VIP RD VIN RDN
05728-001
BIAS CELL
VCM VCC
+
VOP
RG
CD
-
VON
RGN
GND
AD8352
Figure 1.
-60 -65
44 42 40 38 36 34 32 30 28 220
APPLICATIONS
Differential ADC drivers Single-ended-to-differential conversion RF/IF gain blocks SAW filter interfacing
HD3 (dBc)
-70 -75 -80 -85 -90 -95 -100 20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
Figure 2. Third Harmonic Distortion (HD3) and IP3 vs. Frequency, Measured Differentially
GENERAL DESCRIPTION
The AD8352 is a high performance differential amplifier optimized for RF and IF applications. It achieves better than 80 dB SFDR performance at frequencies up to 200 MHz, and 65 dB beyond 500 MHz, making it an ideal driver for high speed 12-bit to 16-bit analog-to-digital converters (ADCs). Unlike other wideband differential amplifiers, the AD8352 has buffers that isolate the gain setting resistor (RG) from the signal inputs. As a result, the AD8352 maintains a constant 3 k input resistance for gains of 3 dB to 25 dB, easing matching and input drive requirements. The AD8352 has a nominal 100 differential output resistance. The device is optimized for wideband, low distortion performance at frequencies beyond 500 MHz. These attributes, together with its wide gain adjust capability, make this device the amplifier of choice for general-purpose IF and broadband applications where low distortion, noise, and power are critical. It is ideally suited for driving not only ADCs but also mixers, pin diode attenuators, SAW filters, and multi-element discrete devices. The device is available in a compact 3 mm x 3 mm, 16-lead LFCSP and operates over a temperature range of -40C to +85C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-2008 Analog Devices, Inc. All rights reserved.
05728-002
IP3 (dBm)
AD8352 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Noise Distortion Specifications .................................................. 4 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Applications Information .............................................................. 11 Gain and Distortion Adjustment (Differential Input) .......... 11 Single-Ended Input Operation ................................................. 12 Narrow-Band, Third-Order Intermodulation Cancellation. 13 High Performance ADC Driving ............................................. 14 Layout and Transmission Line Effects..................................... 15 Evaluation Board ............................................................................ 16 Evaluation Board Loading Schemes ........................................ 16 Soldering Information ............................................................... 16 Evaluation Board Schematics ................................................... 17 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/08--Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Figure 21 ...................................................................... 10 Changes to Table 9 .......................................................................... 16 Added Soldering Information Section......................................... 16 Changes to Figure 38 ...................................................................... 17 Changes to Ordering Guide .......................................................... 19 9/06--Rev. 0 to Rev. A Changes to Absolute Maximum Ratings ....................................... 6 Inserted Figure 10, Figure 11, and Figure 13 ................................ 9 Inserted Figure 17, Figure 18, and Figure 21 .............................. 10 Changes to Figure 34 ...................................................................... 14 Changes to Table 9 .......................................................................... 16 Changes to Figure 38 ...................................................................... 18 Changes to Ordering Guide .......................................................... 19 1/06--Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8352 SPECIFICATIONS
VS = 5 V, RL = 200 differential, RG = 118 (AV = 10 dB), f = 100 MHz, T = 25C; parameters specified differentially (in/out), unless otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6). Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions AV = 6 dB, VOUT 1.0 V p-p AV = 10 dB, VOUT 1.0 V p-p AV = 14 dB, VOUT 1.0 V p-p 3 dB AV 20 dB, VOUT 1.0 V p-p 3 dB AV 20 dB, VOUT 1.0 V p-p Using 1% resistor for RG, 0 dB AV 20 dB VS 5% -40C to +85C RL = 1 k, VOUT = 2 V step RL = 200 , VOUT = 2 V step 2 V step to 1% VIN = 4 V to 0 V step, VOUT 10 mV Min Typ 2500 2200 1800 190 300 1 0.06 4 9 8 <2 <3 -80 VCC/2 1.2 to 3.8 6 -100 0.25 -20 -40C to +85C 57 0.15 5 3 0.9 100 3 3 ENB at 3 V ENB at 0.6 V ENB at 3 V ENB at 0.6 V 5 1.5 75 -125 37 5.3 5.5 +20 +20 Max Unit MHz MHz MHz MHz MHz dB dB/V mdB/C V/ns V/ns ns ns dB V V V p-p mV mV/C mV dB mV/C A k pF pF V V nA A mA mA
Bandwidth for 0.1 dB Flatness Bandwidth for 0.2 dB Flatness Gain Accuracy Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12) INPUT/OUTPUT CHARACTERISTICS Common-Mode Nominal Voltage Adjustment Range Maximum Output Voltage Swing Output Common-Mode Offset Output Common-Mode Drift Output Differential Offset Voltage Common-Mode Rejection Ratio (CMRR) Output Differential Offset Drift Input Bias Current Input Resistance Input Capacitance (Single Ended) Output Resistance Output Capacitance POWER INTERFACE Supply Voltage ENB Threshold ENB Input Bias Current Quiescent Current
1 dB compressed Referenced to VCC/2 -40C to +85C
35
39
Rev. B | Page 3 of 20
AD8352
NOISE DISTORTION SPECIFICATIONS
VS = 5 V, RL = 200 differential, RG = 118 (AV = 10 dB), VOUT = 2 V p-p composite, T = 25C; parameters specified differentially, unless otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6). See the Applications Information section for single-ended-to-differential performance characteristics. Table 2.
Parameter 10 MHz Second/Third Harmonic Distortion 1 Output Third-Order Intercept Third-Order IMD Conditions RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 9.5 MHz, f2 = 10.5 MHz RL = 1 k, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite Min Typ -88/-95 -86/-82 38 -86 -81 2.7 15.7 RL = 1 k, RG = 178 , VOUT = 2 V p-p RL = 200 , RG = 115 , VOUT = 2 V p-p RL = 200 , f1 = 69.5 MHz, f2 = 70.5 MHz RL = 1 k, f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite -83/-84 -84/-82 40 -91 -83 2.7 15.7 RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 99.5 MHz, f2 = 100.5 MHz RL = 1 k, f1 = 99.5 MHz, f2 = 100.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 99.5 MHz, f2 = 100.5 MHz, VOUT = 2 V p-p composite -83/-83 -84/-82 40 -91 -84 2.7 15.6 RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 139.5 MHz, f2 = 140.5 MHz RL = 1 k, f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p composite -83/-82 -82/-84 41 -89 -85 2.7 15.5 Max Unit dBc dBc dBm dBc dBc nV/Hz dBm dBc dBc dBm dBc dBc nV/Hz dBm dBc dBc dBm dBc dBc nV/Hz dBm dBc dBc dBm dBc dBc nV/Hz dBm
Noise Spectral Density (RTI) 1 dB Compression Point (RTO) 70 MHz Second/Third Harmonic Distortion Output Third-Order Intercept Third-Order IMD
Noise Spectral Density (RTI) 1 dB Compression Point (RTO) 100 MHz Second/Third Harmonic Distortion Output Third-Order Intercept Third-Order IMD
Noise Spectral Density (RTI) 1 dB Compression Point (RTO) 140 MHz Second/Third Harmonic Distortion Output Third-Order Intercept Third-Order IMD
Noise Spectral Density (RTI) 1 dB Compression Point (RTO)
Rev. B | Page 4 of 20
AD8352
Parameter 190 MHz Second/Third Harmonic Distortion Output Third-Order Intercept Third-Order IMD Conditions RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 180.5 MHz, f2 = 190.5 MHz RL = 1 k, f1 = 180.5 MHz, f2 = 190.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 180.5 MHz, f2 = 190.5 MHz, VOUT = 2 V p-p composite Min Typ -82/-85 -81/-87 39 -83 -81 2.7 15.4 RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 239.5 MHz, f2 = 240.5 MHz RL = 1 k, f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite -82/-76 -80/-73 36 -85 -77 2.7 15.3 RL = 1 k, VOUT = 2 V p-p RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 379.5 MHz, f2 = 380.5 MHz RL = 1 k, f1 = 379.5 MHz, f2 = 380.5 MHz, VOUT = 2 V p-p composite RL = 200 , f1 = 379.5 MHz, f2 = 380.5 MHz, VOUT = 2 V p-p composite -72/-68 -74/-69 33 -74 -70 2.7 14.6 RL = 200 , VOUT = 2 V p-p RL = 200 , f1 = 499.5 MHz, f2 = 500.5 MHz RL = 200 , f1 = 499.5 MHz, f2 = 500.5 MHz, VOUT = 2 V p-p composite -71/-64 28 -61 2.7 13.9 Max Unit dBc dBc dBm dBc dBc nV/Hz dBm dBc dBc dBm dBc dBc nV/Hz dBm dBc dBc dBm dBc dBc nV/Hz dBm dBc dBm dBc nV/Hz dBm
Noise Spectral Density (RTI) 1 dB Compression Point (RTO) 240 MHz Second/Third Harmonic Distortion Output Third-Order Intercept Third-Order IMD
Noise Spectral Density (RTI) 1 dB Compression Point (RTO) 380 MHz Second/Third Harmonic Distortion 2 Output Third-Order Intercept Third-Order IMD
Noise Spectral Density (RTI) 1 dB Compression Point (RTO) 500 MHz Second/Third Harmonic Distortion2 Output Third-Order Intercept Third-Order IMD Noise Spectral Density (RTI) 1 dB Compression Point (RTO)
1
When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer, such as Mini-Circuits(R) ADT1-1WT to obtain the low frequency balance required for differential HD2 cancellation. 2 CD and RD can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, CD and RD components are not required.
Rev. B | Page 5 of 20
AD8352 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage, VCC VIP, VIN Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 5.5 V VCC + 0.5 V 210 mW 91.4C/W 125C -40C to +85C -65C to +150C 300C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. B | Page 6 of 20
AD8352 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 ENB 14 VCM 16 VIP 13 VCC
RDP 1 RGP 2 RGN 3 RDN 4
PIN 1 INDICATOR
12 GND 11 VOP 10 VON 9 GND
AD8352
TOP VIEW (Not to Scale)
GND 7
GND 6
VCC 8
VIN 5
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6, 7, 9, 12 8, 13 10 11 14 Mnemonic RDP RGP RGN RDN VIN GND VCC VON VOP VCM Description Positive Distortion Adjust. Positive Gain Adjust. Negative Gain Adjust. Negative Distortion Adjust. Balanced Differential Input. This pin is biased to VCM, typically ac-coupled. Ground. Connect this pin to low impedance GND. Positive Supply. Balanced Differential Output. This pin is biased to VCM, typically ac-coupled. Balanced Differential Output. This pin is biased to VCM, typically ac-coupled. Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output. Typically decoupled to ground with a 0.1 F capacitor. With no reference applied, input and output common mode floats to midsupply (VCC/2). Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. Balanced Differential Input. This pin is biased to VCM, typically ac-coupled.
15 16
ENB VIP
Rev. B | Page 7 of 20
05728-003
AD8352 TYPICAL PERFORMANCE CHARACTERISTICS
25 30 25 RG = 43 20 15 20 RG = 20
GAIN (dB)
GAIN (dB)
RG = 100 10 RG = 520 5
15 10 5
RG = 100 RG = 182 RG = 383 RG = 715
0
0 -5 10
05728-036
100
1k
10k
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Gain vs. Frequency for a 200 Differential Load with Baluns, AV = 18 dB, 12 dB, and 6 dB
25
Figure 7. Gain vs. Frequency for a 1 k Differential Load Without Baluns, RD/CD Open, AV = 25 dB, 14 dB, 10 dB, 6 dB, and 3 dB
13.0 12.5 -40C +85C 11.0 10.5 10.0 +25C 9.5
GAIN (dB)
05728-043 05728-040
20
RG = 62
RL = 1k RG = 182 TC = 0.002dB/C
12.0 11.5
GAIN (dB)
15
GAIN (dB)
RG = 190 10 RG = 3k 5
11.0 10.5 10.0 9.5 9.0 8.5 +85C RL = 200 RG = 118 TC = 0.004dB/C +25C -40C
9.0 8.5 8.0 7.5 7.0 6.5 100 1k 6.0 10k
0
100
1k
10k
FREQUENCY (MHz)
05728-037
-5 10
8.0 10
FREQUENCY (MHz)
Figure 5. Gain vs. Frequency for a 1 k Differential Load with Baluns, AV = 18 dB, 12 dB, and 6 dB
25 RG = 19
Figure 8. Gain vs. Frequency over Temperature (-40C, +25C, +85C) Without Baluns, AV = 10 dB, RL = 200 and 1 k
80 70 RL = 200 60
20
15
RG = 64
CMRR (dB)
GAIN (dB)
10
RG = 118 RG = 232
50 40 30 20 10 10
RL = 1k
5 RG = 392 0
100
1k
10k
05728-038
-5 10
100 FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency for a 200 Differential Load Without Baluns, RD/CD Open, AV = 22 dB, 14 dB, 10 dB, 6 dB, and 3 dB
Figure 9. CMRR vs. Frequency, RL = 200 and 1 k, Differential Source Resistance
Rev. B | Page 8 of 20
05728-039
-5 10
AD8352
50 45
NOISE FIGURE (dB), OIP3 (dBm)
5.0
SPECTRAL NOISE DENSITY RTI (nV/ Hz)
16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 190MHz 240MHz 70MHz 100MHz 140MHz
4.5 OIP3 AV = 10dB 4.0 AV = 15dB 3.5 AV = 6dB 3.0 2.5 AV = 10dB AV = 10dB 2.0 1.5 1.0 500
40 35 30 25 20 15 10
OUTPUT P1dB (dBm)
380MHz
500MHz
NOISE FIGURE
0
50
100
150
200
250
300
350
400
450
05728-049
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
GAIN SETTING RESISTOR ()
Figure 10. Noise Figure, OIP3, and Spectral Noise Density vs. Frequency, 2 V p-p Composite, RL = 200
45 70MHz 40 240MHz
OIP3 (dBm)
Figure 13. Output 1 dB Compression Point (P1dB) vs. RG for Multiple Frequencies, RL = 200
-60
140MHz
100MHz
-65
HARMONIC DISTORTION (dBc)
190MHz
-70 -75 -80 -85 -90 -95 -100 -105 0 50 100 150 200 250
HD3
35
380MHz
HD2
30
500MHz
25
05728-050
300
350
400
450
500
GAIN SETTING RESISTOR ()
FREQUENCY (MHz)
Figure 11. Output IP3 (OIP3) vs. RG for Multiple Frequencies, RL = 200
Figure 14. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 k, AV = 10 dB, 5 V Supply, RG = 180 , RD = 6.8 k, CD = 0.1 pF
-50
-60 > 300MHz NO CD OR RD USED HARMONIC DISTORTION (dBc)
-70
HD3 2V p-p HD2 2V p-p
HARMONIC DISTORTION (dBc)
-65
-60
-70
HD3
-75
-80
HD2
-80 HD3 1V p-p
-90
-85
-100
05728-009
220
260
300
340
380
420
460
500
0
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Third-Order Harmonic Distortion (HD3) vs. Frequency, AV = 10 dB, RL = 200
Figure 15. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 200 , AV = 10 dB, RG = 115 , RD = 4.3 k, CD = 0.2 pF
Rev. B | Page 9 of 20
05728-007
-90
-110
05728-005
20
0
50
100
150
200
250
300
350
400
-110
05728-051
AD8352
0.6 0 1.5
tRISE (10/90) = 215ps tFALL (10/90) = 210ps
0.5
-20
1.0
GROUP DELAY (ns)
PHASE (Degrees)
VOLTAGE (V)
0.4
-40
0.5
0.3
-60
0
0.2
-80
-0.5
0.1
-100
-1.0
0
100
200
300
400
500
600
700
800
900
05728-042
0
0.5
1.0
1.5 TIME (nsec)
2.0
2.5
3.0
FREQUENCY (MHz)
Figure 16. Group Delay and Phase vs. Frequency, AV = 10 dB, RL = 200
Figure 19. Large Signal Output Transient Response, RL = 200 , AV = 10 dB.
3500 3000
INPUT RESISTANCE ()
0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 1000
05728-052
5 4 3
2500 2000 1500 1000 500 0
INPUT CAPACITANCE (pF)
2
SETTLING (%)
1 0 -1 -2 -3 -4 0 0.5 1.0 1.5 2.0 TIME (nsec) 2.5 3.0 3.5 4.0
05728-047
0
100
200
300
400
500
600
700
800
900
-5
FREQUENCY (MHz)
Figure 17. S11 Equivalent RC Parallel Network, RG = 115
Figure 20. 1% Settling Time for a 2 V p-p Step Response, AV = 10 dB, RL = 200
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
OUTPUT CAPACITANCE (pF)
160 140
OUTPUT RESISTANCE ()
6 SPECTRAL NOISE DENSITY RTI (nV/ Hz)
25
5 20 4 NOISE FIGURE (dB)
05728-054
120 100 80 60 40 20 0
3
15
2 10 1
0
100
200
300
400
500
600
700
800
900
-1.0 1000
05728-053
0
0
50
100
150
200
250
300
350
400
5
FREQUENCY (MHz)
GAIN SETTING RESISTOR ()
Figure 18. S22 Equivalent RC Parallel Network, RG = 115
Figure 21. Spectral Noise Density RTI and Noise Figure vs. RG, RL = 200
Rev. B | Page 10 of 20
05728-046
0
-120 1000
-1.5
AD8352 APPLICATIONS INFORMATION
GAIN AND DISTORTION ADJUSTMENT (DIFFERENTIAL INPUT)
Table 5 and Table 6 show the required value of RG for the gains specified at 200 and 1 k loads. Figure 22 and Figure 24 plot gain vs. RG up to 18 dB for both load conditions. For other output loads (RL), use Equation 1 to compute gain vs. RG. Table 6. Broadband Selection of RG, CD, and RD, 1 k Load
AV (dB) 3 6 9 10 12 15 18
20 18 16 14
RG + 500 AV Differential = (R + 5) (R + 53) + 430 RL L G
where RL is the single-ended load. RG is the gain setting resistor.
(1)
RG () 750 360 210 180 130 82 54
CD (pF) Open Open Open 0.05 0.1 0.3 0.5
RD (k) 6.8 6.8 6.8 6.8 6.8 6.8 6.8
The third-order harmonic distortion can be reduced by using external components RD and CD. Table 5 and Table 6 show the required values for RD and CD for the specified gains to achieve (single tone) third-order distortion reduction at 180 MHz. Figure 23 and Figure 25 show any gain (up to 18 dB) vs. CD for 200 and 1 k loads, respectively. When these values are selected, they result in minimum single tone, third-order distortion at 180 MHz. This frequency point provides the best overall broadband distortion for the specified frequencies below and above this value. For applications above ~300 MHz, CD and RD are not required. See the Specifications section and the third-order harmonic plots for more details (see Figure 12, Figure 14, and Figure 15). CD can be further optimized for narrow-band tuning requirements below 180 MHz that result in relatively lower third-order (inband) intermodulation distortion terms. See the Narrow-Band, Third-Order Intermodulation Cancellation section for more information. Though not shown, single tone, third-order optimization can also be improved for narrow-band frequency applications below 180 MHz with the proper selection of CD, and 3 dB to 6 dB of relative third-order improvement can be realized at frequencies below approximately 140 MHz. Using the information listed in Table 5 and Table 6, an extrapolated value for RD can be determined for loads between 200 and 1 k. For loads above 1 k, use the 1 k RD values listed in Table 6.
Table 5. Broadband Selection of RG, CD, and RD, 200 Load
AV (dB) 3 6 9 10 12 15 18 RG () 390 220 140 115 86 56 35 CD (pF) Open Open 0.1 0.2 0.3 0.6 1 RD (k) 6.8 4.3 4.3 4.3 4.3 4.3 4.3
GAIN (dB)
12 10 8 6 4 2 0
05728-026
05728-027
0
50
100
150
200 RG ()
250
300
350
400
Figure 22. Gain vs. RG, RL = 200
20 18 16 14
GAIN (dB)
12 10 8 6 4 2 0 0 0.1 0.2 0.3 0.4 0.5 CD (pF) 0.6 0.7 0.8 0.9 1.0
Figure 23. Gain vs. CD, RL = 200
Rev. B | Page 11 of 20
AD8352
20 18 16 14
GAIN (dB)
12 10 8 6 4 2 0
Figure 27 plots gain vs. RG for 200 and 1 k loads. Table 7 and Table 8 show the values of CD and RD required (for 180 MHz broadband, third-order, single tone optimization) for 200 and 1 k loads, respectively. This single-ended configuration provides -3 dB bandwidths similar to input differential drive. Figure 28 through Figure 31 show distortion levels at a gain of 12 dB for both 200 and 1 k loads. Gains from 3 dB to 18 dB, using optimized CD and RD values, obtain similar distortion levels.
0.1F VIP RGP CD 0.1F AC
05728-024
0.1F
50
05728-028
65 RD RG
0
100
200
300
400 RG ()
500
600
700
800
AD8352
RGN
Figure 24. Gain vs. RG, RL = 1 k
20 18 16 14
25
RN 200
0.1F
Figure 26. Single-Ended Schematic
40 35 30 25
GAIN (dB)
12 10 8 6 4 2 0
05728-029
GAIN (dB)
20 15
GAIN, RL = 1k
GAIN, RL = 200
0
0.1
0.2 CD (pF)
0.3
0.4
0.5
10 5 0
Figure 25. Gain vs. CD, RL = 1 k
SINGLE-ENDED INPUT OPERATION
The AD8352 can be configured as a single-ended-to-differential amplifier, as shown in Figure 26. To balance the outputs when driving the VIP input, an external resistor (RN) of 200 is added between VIP and RGN. See Equation 2 to determine the singleended input gain (AV Single-Ended) for a given RG or RL.
RG+ 500 AV Single - Ended = (R + 5 ) (R + 53) + 430 L G RL RL + RL + 30
1
10
100 RG ()
1k
10k
Figure 27. Gain vs. RG
-60
-70
2V p-p OUT
(2)
HD2 (dBc)
-80 1V p-p OUT
where RL is the single-ended load. RG is the gain setting resistor.
-90
-100
10
70
140 FREQUENCY (MHz)
190
240
Figure 28. Single-Ended, Second-Order Harmonic Distortion (HD2) vs. Frequency, 200 Load
Rev. B | Page 12 of 20
05728-021
-110
05728-020
AD8352
This broadband optimization was also performed at 180 MHz. As with differential input drive, the resulting distortion levels at lower frequencies are based on the CD and RD specified in Table 7 and Table 8. As with differential input drive, relative third-order reduction improvement at frequencies below 140 MHz is realized with proper selection of CD and RD.
-60
Table 7. Distortion Cancellation Selection Components (RD and CD) for Required Gain, 200 Load
AV (dB) 3 6 9 12 15 18 RG () 4.3 k 540 220 120 68 43 CD (pF) Open Open 0.1 0.3 0.6 0.9 RD (k) 4.3 4.3 4.3 4.3 4.3 4.3
-70 2V p-p OUT
HD3 (dBc)
-80
Table 8. Distortion Cancellation Selection Components (RD and CD) for Required Gain, 1 k Load
1V p-p OUT
-90
-100
10
70
140 FREQUENCY (MHz)
190
240
05728-022
-110
AV (dB) 6 9 12 15 18
RG () 3k 470 210 120 68
CD (pF) Open Open 0.2 0.3 0.5
RD (k) 4.3 4.3 4.3 4.3 4.3
Figure 29. Single-Ended, Third-Order Harmonic Distortion (HD3) vs. Frequency, 200 Load
-60
NARROW-BAND, THIRD-ORDER INTERMODULATION CANCELLATION
Broadband single tone, third-order harmonic optimization does not necessarily result in optimum (minimum) two tone, thirdorder intermodulation levels. The specified values for CD and RD in Table 5 and Table 6 were determined for minimizing broadband, single tone third-order levels.
-70
HD2 (dBc)
-80 2V p-p OUT -90
-100
1V p-p OUT
10
70
140 FREQUENCY (MHz)
190
240
05728-023
-110
Due to phase-related distortion coefficients, optimizing single tone third-order distortion does not result in optimum in-band (2f1 - f2 and 2f2 - f1), third-order distortion levels. By proper selection of CD (using a fixed 4.3 k RD), IP3s of better than 45 dBm are achieved. This results in degraded out-of-band, third-order frequencies (f2 + 2f1, f1 + 2f2, 3f1 and 3f2). Thus, careful frequency planning is required to determine the trade-offs. Figure 32 shows narrow-band (2 MHz spacing) OIP3 levels optimized at 32 MHz, 70 MHz, 100 MHz, and 180 MHz using the CD values specified in Figure 33. These four data points (the CD value and associated OIP3 levels) are extrapolated to provide close estimates of OIP3 levels for any specific frequency between 30 MHz and 180 MHz. For frequencies below ~140 MHz, narrowband tuning of OIP3 results in relatively higher OIP3s (vs. the broadband results shown in Table 2 of the specifications). Though not shown, frequencies below 30 MHz also result in improved OIP3s when using proper values for CD.
Figure 30. Single-Ended, Second-Order Harmonic Distortion (HD2) vs. Frequency, 1 k Load
-60
-70
HD3 (dBc)
-80
2V p-p OUT
-90 1V p-p OUT -100
10
70
140 FREQUENCY (MHz)
190
240
Figure 31. Single-Ended, Third-Order Harmonic Distortion (HD3) vs. Frequency, 1 k Load
Rev. B | Page 13 of 20
05728-025
-110
AD8352
48 47 46 45 OIP3 (dBm) 44 43 42 41 40 39 0 50 100 FREQUENCY (MHz) 150 200
05728-030
RL = 200 RD = 4.3k CD = 0.3pF
AV =
6dB 10dB 15dB 18dB
38
Refer to the Layout and Transmission Line Effects section for more information. The circuit in Figure 35 represents a singleended input to differential output configuration for driving the AD9445. In this case, the input 50 resistor with RN (typically 200 ) provide the input impedance match for a 50 system. Again, if input reflections are minimal, this impedance match is not required. A fixed 200 resistor (RN) is required to balance the output voltages that are required for second-order distortion cancellation. RG is the gain setting resistor for the AD8352 with the RD and CD components providing distortion cancellation. The AD9445 presents approximately 2 k in parallel with 5 pF/differential load to the AD8352 and requires a 2.0 V p-p differential signal (VREF = 1 V) between VIN+ and VIN- for a full-scale output operation. These AD8352 simplified circuits provide the gain, isolation, and distortion performance necessary for efficiently driving high linearity converters, such as the AD9445. This device also provides balanced outputs whether driven differentially or singleended, thereby maintaining excellent second-order distortion levels. However, at frequencies above ~100 MHz, due to phaserelated errors, single-ended, second-order distortion is relatively higher. The output of the amplifier is ac-coupled to allow for an optimum common-mode setting at the ADC input. Input ac coupling can be required if the source also requires a commonmode voltage that is outside the optimum range of the AD8352. A VCM common-mode pin is provided on the AD8352 that equally shifts both input and output common-mode levels. Increasing the gain of the AD8352 increases the system noise and, thus, decreases the SNR (3.5 dB at 100 MHz input for Av = 10 dB) of the AD9445 when no filtering is used. Note that amplifier gains from 3 dB to 18 dB, with proper selection of CD and RD, do not appreciably affect distortion levels. These circuits, when configured properly, can result in SFDR performance of better than 87 dBc at 70 MHz and 82 dBc at 180 MHz input. Single-ended drive, with appropriate CD and RD, give similar results for SFDR and thirdorder intermodulation levels shown in these figures. Placing antialiasing filters between the ADC and the amplifier is a common approach for improving overall noise and broadband distortion performance for both band-pass and low-pass applications. For high frequency filtering, matching to the filter is required. The AD8352 maintains a 100 output impedance well beyond most applications and is well-suited to drive most filter configurations with little or no degradation in distortion.
Figure 32. Third-Order Intermodulation Distortion, OIP3 vs. Frequency for Various Gain Settings
6.0 5.5 5.0 4.5 4.0 CD (pF) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 50 70 90 110 130 150 170 190
05728-031
RL = 200 RD = 4.3k
AV =
6dB 10dB 15dB 18dB
0 30
FREQUENCY (MHz)
Figure 33. Narrow-Band CD vs. Frequency for Various Gain Settings
HIGH PERFORMANCE ADC DRIVING
The AD8352 provides the gain, isolation, and balanced low distortion output levels for efficiently driving wideband ADCs such as the AD9445. Figure 34 and Figure 35 (single and differential input drive) illustrate the typical front-end circuit interface for the AD8352 differentially driving the AD9445 14-bit ADC at 105 MSPS. The AD8352, when used in the single-ended configuration, shows little or no degradation in overall third-order harmonic performance (vs. differential drive). See the Single-Ended Input Operation section. The 100 MHz FFT plots shown in Figure 36 and Figure 37 display the results for the differential configuration. Though not shown, the single-ended, third-order levels are similar. The 50 resistor shown in Figure 34 provides a 50 differential input impedance to the source for matching considerations. When the driver is less than one eighth of the wavelength from the AD8352, impedance matching is not required thereby negating the need for this termination resistor. The output 24 resistors provide isolation from the analog-to-digital input.
Rev. B | Page 14 of 20
AD8352
VCC 0.1F 0 16
1 2 8, 13 11
0 -10 -20 -30 -40
0.1F
SNR = 61.98dBc NOISE FLOOR = -111.2dB FUND1 = -7.072dBFS FUND2 = -7.043dBFS IMD (2F2-F1) = -89dBc IMD (2F1-F2) = -88dBc
AMPLITUDE (dBFS)
0.1F 24
IF/RF INPUT 50 ADT1-1WT RD
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 FREQUENCY (MHz)
05728-035
CD
RG
3 4 5
AD8352
10 14
AD9445
0.1F 24
05728-012
0.1F
0
0.1F
Figure 34. Differential Input to the AD8352 Driving the AD9445
0.1F 50 AC 50 CD RD RG VIN 0.1F VON RN 200 0.1F 0.1F 33 VOP VIN+
-150
VIP
AD8352
33
AD9445
VIN-
Figure 37. Two Tone Distortion AD8352 Driving AD9445, Encode Clock @ 105 MHz with fC @ 100 MHz (AV = 10 dB), Analog In = 98 MHz and 101 MHz, See Figure 34
LAYOUT AND TRANSMISSION LINE EFFECTS
High Q inductive drives and loads, as well as stray transmission line capacitance in combination with package parasitics, can potentially form a resonant circuit at high frequencies resulting in excessive gain peaking or possible oscillation. If RF transmission lines connecting the input or output are used, they should be designed such that stray capacitance at the input/output pins is minimized. In many board designs, the signal trace widths should be minimal where the driver/ receiver is more than one-eighth of the wavelength from the AD8352. This nontransmission line configuration requires that underlying and adjacent ground and low impedance planes be dropped from the signal lines. In a similar fashion, stray capacitance should be minimized near the RG, CD, and RD components and associated traces. This also requires not placing low impedance planes near these components. Refer to the evaluation board layout (Figure 39 and Figure 40) for more information. Excessive stray capacitance at these nodes results in unwanted high frequency distortion. The 0.1 F supply decoupling capacitors need to be close to the amplifier. This includes Signal Capacitor C2 through Signal Capacitor C5. Parasitic suppressing resistors (R5, R6, R7, and R11) can be used at the device input/output pins. Use 25 series resistors (Size 0402) to adequately de-Q the input and output system from most parasitics without a significant decrease in gain. In general, if proper board layout techniques are used, the suppression resistors are not necessarily required. Output Parasitic Suppression Resistor R7 and Output Parasitic Suppression Resistor R11 can be required for driving some switch capacitor ADCs. These suppressors, with Input C of the converter (and possibly added External Shunt C), help provide charge kickback isolation and improve overall distortion at high encode rates.
05728-033
05728-034
25
Figure 35. Single-Ended Input to the AD8352 Driving the AD9445
0 -10 -20 -30 -40 SNR = 67.26dBc SFDR = 83.18dBc NOISE FLOOR = -110.5dB FUND = -1.074dBFS SECOND = -83.14dBc THIRD = -85.39dBc
AMPLITUDE (dBFS)
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 FREQUENCY (MHz)
Figure 36. Single Tone Distortion AD8352 Driving AD9445, Encode Clock @ 105 MHz with fC @ 100 MHz (AV = 10 dB), See Figure 34
Rev. B | Page 15 of 20
AD8352 EVALUATION BOARD
An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are shown in Figure 38, Figure 39, and Figure 40. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B).
Table 9. Evaluation Board Circuit Components and Functions
Component C8, C9, C10 RD, CD Name Capacitors Distortion tuning components Function C8, C9, and C10 are bypass capacitors. Distortion Adjustment Components. Allows for third-order distortion adjustment HD3. Additional Information C8 = C9 = C10 = 0.1 F Typically, both are open above 300 MHz CD = 0.2 pF, RD = 4.32 k CD is Panasonic High-Q (microwave) multilayer chip 402 capacitor R1 = open, R2 = 25 , R3 = 25 , R4 = 0 , R5 = 0 , R6 = 0 , T2 = M/A-COM ETC1-1-13, C2 = 0.1 F, C3 = 0.1 F R7 = 0 , R8 = 86.6 , R9 = 57.6 , R11 = 0 , R12 = 86.6 , R13 = 0 , R14 = open, T1 = M/A-COM ETC1-1-13, C4 = 0.1 F, C5 = 0.1 F
R1, R2, R3, R4, R5, R6, T2, C2, C3
Resistors, transformer, capacitors
R7, R8, R9, R11, R12, R13, R14, T1, C4, C5
Resistors, transformer, capacitors
RG SW1, R18, R19, R20 C1, C6, C7 T3, T4, C11, C12
Resistor Switch, resistors Capacitors Transformer, capacitors
Input Interface. R1 and R4 ground one side of the differential drive interface for single-ended applications. T2 is a 1-to-1 impedance ratio balun to transform a single-ended input into a balanced differential signal. R2 and R3 provide a differential 50 input termination. R5 and R6 can be increased to reduce gain peaking when driving from a high source impedance. The 50 termination provides an insertion loss of 6 dB. C2 and C3 provide ac-coupling. Output Interface. R13 and R14 ground one side of the differential output interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun to transform a balanced differential signal to a single-ended signal. R8, R9, and R12 are provided for generic placement of matching components. R7 and R11 allow additional output series resistance when driving capacitive loads. The evaluation board is configured to provide a 200 to 50 impedance transformation with an insertion loss of 11.6 dB. C4 and C5 provide ac-coupling. R7 and R11 provide additional series resistance when driving capacitive loads. Gain Setting Resistor. Resistor RG is used to set the gain of the device. Refer to Table 5 and Table 6 when selecting the gain resistor. Enable Interface. R10 connects the enable pin, ENB, to the supply for constant enable operation. The enable function can be toggled by removing R10 and using SW1 to switch between enable and disable modes. Power Supply Decoupling. The supply decoupling consists of a 10 F capacitor (C1) to ground. C6 and C7 are bypass capacitors. Calibration Circuit. T3 and T4 are dummy baluns which may be used to calibrate the insertion loss across the transformers in the AD8352 signal chain.
RG = 115 (Size 0402) for a gain of 10 dB SW1 = installed R18 = R19 = R20 = 0 C1 = 10 F, C6 = 0.1 F, C7 = 0.1 F T3 = T4 = M/A-COM ETC1-1-13 C11 = C12 = 0.1 F
EVALUATION BOARD LOADING SCHEMES
The AD8352 evaluation board is characterized with two load configurations representing the most common ADC input resistance. The loads chosen are 200 and 1000 using a broadband resistive match. The loading can be changed via R8, R9, and R12 giving the flexibility to characterize the AD8352 evaluation board for the load in any given application. These loads are inherently lossy and thus must be accounted for in overall gain/loss for the entire evaluation board. Measure the gain of the AD8352 with an oscilloscope using the following procedure to determine the actual gain: 1. Measure the peak-to-peak voltage at the input node (C2 or C3). 2. Measure the peak-to-peak voltage at the output node (C4 or C5). 3. Compute gain using the following formula: Gain = 20log(VOUT/VIN)
Table 10. Values Used for 200 and 1000 Loads
Component R8 R9 R12 200 Load () 86.6 57.6 86.6 1000 Load () 487 51.1 487
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed compressed paddle. This paddle is internally connected to the ground of the chip. Solder the paddle to the low impedance ground plane on the PCB to ensure the specified electrical performance and to provide thermal relief. To further reduce thermal impedance, it is recommended that the ground planes on all layers under the paddle be stitched together with vias.
Rev. B | Page 16 of 20
VCM ENBL YELLOW SWITCH_SPDT R18 0 C8 0.1F VPOS VOUTP GND R7 0 C4 0.1F R8 86.6
5 1
VPOS SW1 R20 0 C9 0.1F BLACK ENB
EVALUATION BOARD SCHEMATICS
R19 0 YELLOW VCM GND C10 0.1F
ENB
VCM
14 12 11 VOP
R1 OPEN
3 2 4
R2 25 RGP 2 CD 0.2pF RD 4.32k RG 115 RGN 3 VON
10 9
RDP 1 16
15
VCC
13
VINP VIP
C2 0.1F R5 0
R14 OPEN R9 57.6 T1
4 2 3
T2
1 5
Z1
RDN 4 GND
5 6 7 8
GND
05728-017
Figure 38. AD8352 Evaluation Board, Version A01212A
Rev. B | Page 17 of 20
R4 0 R3 25
C3 0.1F
R6 0
VIN VPOS
GND
VCC
VINN
M/A_COM ETC1-1-13
AD8352
R11 0
C5 0.1F
R12 86.6
M/A_COM ETC1-1-13
VOUTN R13 0
50 TRACES
HIGH IMPEDANCE TRACES (OPEN PLANES UNDER TRACES)
50 TRACES
CALIBRATION CIRCUIT
J1 J2
VPOS RED
BYPASS CIRCUIT
VPOS
5 1
5
1
C11 0.1F T4 C12 0.1F
4 2 3
+
T3
4 2 3
C1 10F
C6 0.1F
C7 0.1F
LOCATE CAPS NEAR DUT
AD8352
AD8352
Figure 39. Component Side Silkscreen
Figure 40. Far Side Showing Ground Plane Pull Back Around Critical Features
Rev. B | Page 18 of 20
05728-019
05728-018
AD8352 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.60 MAX 0.50 0.40 0.30
13 12
16
EXPOSED PAD
1
PIN 1 INDICATOR *1.65 1.50 SQ 1.35
9 (BOTTOM VIEW) 4 8 5
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8352ACPZ-WP 1 AD8352ACPZ-R71 AD8352ACPZ-R21 AD8352-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel Evaluation Board
Ordering Quantity 50 3000 250
Package Option CP-16-3 CP-16-3 CP-16-3
Branding Q0R Q0R Q0R
Z = RoHS Compliant Part.
Rev. B | Page 19 of 20
AD8352 NOTES
(c)2006-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05728-0-7/08(B)
Rev. B | Page 20 of 20

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